IMPLEMENTASI MASKED FACE RECOGNITION MENGGUNAKAN FPGA SEBAGAI HARDWARE ACCELERATOR DENGAN ALGORITMA Tiny YOLOv3-Submit Jurnal

Rahmat, Zaky Nur (2025) IMPLEMENTASI MASKED FACE RECOGNITION MENGGUNAKAN FPGA SEBAGAI HARDWARE ACCELERATOR DENGAN ALGORITMA Tiny YOLOv3-Submit Jurnal. Bachelor thesis, Institut Teknologi Kalimantan.

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Abstract

Pengenalan wajah bermasker merupakan tantangan dalam sistem identifikasi visual, terutama pada aplikasi real-time di lingkungan publik. Penelitian ini mengembangkan sistem pengenalan wajah bermasker berbasis Tiny YOLOv3 yang diimplementasikan secara real-time dengan akselerasi perangkat keras menggunakan FPGA PYNQ-Z2. Tahap pra-pemrosesan gambar (resize, grayscale, threshold) dilakukan di FPGA menggunakan IP Core hasil rancangan di Vitis HLS, sementara proses inferensi dijalankan di CPU dengan model dalam format ONNX. Pengujian dilakukan pada dua konfigurasi: pemrosesan penuh di CPU dan kombinasi FPGA–CPU. Hasil menunjukkan bahwa sistem dengan FPGA memiliki kecepatan rata-rata 15,49 FPS dan konsumsi daya 14,55 W, lebih baik dibandingkan CPU dengan 11,76 FPS dan konsumsi daya 27,42 W. Confidence Threshold deteksi pada FPGA mencapai 61%, sedikit lebih tinggi dari CPU yang sebesar 58%. Implementasi ini menunjukkan bahwa integrasi FPGA mampu meningkatkan efisiensi sistem baik dari sisi kecepatan maupun konsumsi daya, sehingga layak digunakan untuk aplikasi deteksi real-time yang efisien dan responsif.

Item Type:	Thesis (Bachelor)
Subjects:	T Technology > T Technology (General)
Divisions:	Jurusan Teknologi Industri dan Proses > Teknik Elektro
Depositing User:	Zaky Nur Rahmat
Date Deposited:	11 Jul 2025 01:45
Last Modified:	11 Jul 2025 01:45
URI:	http://repository.itk.ac.id/id/eprint/23894

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